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High Efficiency Switch Mode Li-Ion Battery Charger ADP3808
FEATURES
Selectable 3-cell or 4-cell operation Adjustable 4.0 V to 4.5 V per cell High end-of-charge voltage accuracy 0.4% @ 25C 0.6% @ 5C to 55C 0.8% @ 0C to 100C Programmable charge current, including trickle charge Bootstrapped synchronous drive for external N-channel MOSFETs Programmable oscillator frequency
GENERAL DESCRIPTION
The ADP3808 is a complete Li-Ion battery charging controller for 3- or 4-cell battery packs. The device combines accurate final battery charge voltage control with constant current control to simplify the implementation of constant-current, constant-voltage (CCCV) chargers. The final battery charge voltage is programmable between 4.0 V to 4.5 V per cell, allowing the charging of various cell types. The charge current is programmable over a wide range from trickle charging to full charging. The system current sense amplifier includes an ac adapter detection output to signal that the adapter is connected. The bootstrapped synchronous driver controls two N-channel MOSFET transistors for high efficiency charging at a low system cost. The ADP3808 is specified over the extended commercial temperature range of 0C to 100C and is available in a 24-lead LFCSP package.
APPLICATIONS
Portable computers Portable equipment
FUNCTIONAL BLOCK DIAGRAM
VCC
22
EN
8
UVLO AND BIAS
LOW-SIDE DRIVE REGULATOR
DRVREG
19
BST DRVH SW
EN REFERENCE AGND 10 IN CONTROL LOGIC DRVREG
20 21
18 17 16
DRVREG DRVL PGND
RT
5
OSCILLATOR
DRVLSD
CELLSEL 12 BAT 11 3-/4CELL
VTH
15
CSP CSM
REFIN BATADJ COMP
6 7 9
BATTERY VOLTAGE ADJUST
gm
14
gm CHARGE CURRENT SETPOINT
13
SYSM 23 SYSP 24 1V CMP SYS+ CMP 18.25V CMP
CSADJ
4
EXTPWR
ISYS LIMSET
LIMIT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06632-001
1
2
3
ADP3808 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Setting the Charge Current ....................................................... 10 Final Battery Voltage Control ................................................... 11 Oscillator and PWM .................................................................. 11 5.25 V Bootstrap Regulator....................................................... 12 Bootstrapped Synchronous Driver........................................... 12 System Current Sense ................................................................ 12 LIMIT........................................................................................... 13 AC Adaptor Detection............................................................... 13 EN................................................................................................. 13 UVLO........................................................................................... 13 Loop Feed Forward .................................................................... 13 Application Information................................................................ 14 Design Procedure ....................................................................... 14 Battery Voltage Settings............................................................. 14 Inductor Selection.................................................................. 14 Output Capacitor Selection .................................................. 14 Input Capacitor Ripple .......................................................... 14 Decoupling the VCC Pin ...................................................... 14 Current Sense Filtering.......................................................... 14 MOSFET Selection................................................................. 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
6/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADP3808 SPECIFICATIONS
VCC = 20 V, EN = 5 V, REFIN = 3 V, TA = 0C to 100C, unless otherwise noted. 1 Table 1.
Parameter BATTERY VOLTAGE SENSING Accuracy Symbol VBAT Conditions TA = 25C, 13 V VCC 21 V, BATADJ = 0 V or BATADJ = REFIN 5C TA 55C, 13 V VCC 21 V, BATADJ = 0 V or BATADJ = REFIN 13 V VCC 21 V, BATADJ = 0 V or BATADJ = REFIN EN = 0 V 120 VBAT(OV) to COMP < 1 V 0 2.0 BATADJ = 0 V, CELLSEL = 3.3 V BATADJ = REFIN, CELLSEL = 3.3 V BATADJ = 0 V, CELLSEL = 0 V BATADJ = REFIN, CELLSEL = 0 V CSADJ = REFIN, 3.9 V VCS(CM) 21 V CSADJ = 0.2 x REFIN, 3.9 V VCS(CM) 21 V VCM(CS) IB(CSP) IB(CSP,SD) IB(CSM) AV(CS) IB(CSADJ) VCS(OC) tDC VCS(DRVLSD) VCM(SYS) IB(SYSP) IB( SYSM) -8 -20 0 40 0.1 0.1 31.25 1 100 1 32 12.0 13.5 16.0 18.0 +8 +30 VCC 1 2 2 110 Min -0.4 -0.6 -0.8 170 0.2 135 1 Typ Max +0.4 +0.6 +0.8 Unit % % % k A % s
Input Resistance Shutdown Leakage Current Overvoltage Threshold Overvoltage Response Time BATTERY VOLTAGE ADJUST BATADJ Input Range REFIN Input Range 3-Cell Voltage Low 3-Cell Voltage High 4-Cell Voltage Low 4-Cell Voltage High BATTERY CURRENT SENSE AMPLIFIER Accuracy 2 Input Common Mode Range Input Bias Current--Operating Input Bias Current--Shutdown Input Bias Current--CSM Gain CSADJ Bias Current Overcurrent Threshold2 Overcurrent Response Time DRVL Shutdown Threshold SYSTEM CURRENT SENSE AMPLIFIER Input Common Mode Range Input Bias Current, SYSP Input Bias Current, SYSM Voltage Gain ISYS Output Current LIMIT Threshold LIMSET Input Range LIMIT Output Voltage Low LIMIT Propagation Delay Time EXTPWR Current Threshold EXTPWR Voltage Threshold
RBAT IBAT(SD) VBAT(OV) tBAT(OV) VBATADJ VREFIN VBAT VBAT VBAT VBAT
1.0
REFIN 3.5
V V V V V % % V A A A V/V A mV s mV V A A V/V A mV V mV s mV
EN = 0 V
90 VOC > 130 mV to COMP < 1 V
VTH(LIMIT) VLIMSET VOL(LIMIT) tpdl(LIMIT)
SYSP and SYSM to AGND VSYS(CM) = 19 V VSYS(CM) = 19 V VISYS/(VSYSP - VSYSM) VISYS = 2.5 V SYSP to SYSM, LIMSET = 2.5 V ILIMIT = -100 A (SYSP) - (SYSM) rising > 55 mV to LIMIT going low SYSP to SYSM
10 300 0.1 50 5 53 30 1 22.5
49.5 48 0
22 400 1 51.5 58 3.5 75 27.5
VTH(EXTPWR)
VTH(EXTPWR)
17.5
SYSP to AGND
IEXTPWR = -100 A
18.0
18.25 5 1
18.5 50
V mV s
EXTPWR Output Voltage Low EXTPWR Propagation Delay Time
VTH(EXTPWR)
tdpl(EXTPWR )
SYSP Rising > 18.5 V to EXTPWR going low
Rev. 0 | Page 3 of 16
ADP3808
Parameter OSCILLATOR Maximum Frequency Frequency Variation RT Output Voltage Zero Duty Cycle Threshold Maximum Duty Cycle Threshold LOGIC INPUTS (EN, CELLSEL) Input Voltage High Input Voltage Low Input Current HIGH-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Time Propagation Delay Time LOW-SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Time Propagation Delay Time 3 Timeout Delay 4 Symbol Conditions Min Typ Max Unit
fOSC fOSC VRT
RT = 150 k Measured at COMP Measured at COMP
250 1.9
1 290 2 1 2
340 2.1
MHz kHz V V V V V A k ns ns k ns ns ns ns V mA A V mV V mA
VIH VIL IIN
2.0 Inputs = 0 V or 5 V BST to SW = 5 V BST to SW = 5 V BST to SW = 0 V BST to SW = 5 V, CLOAD = 1 nF BST to SW = 5 V, CLOAD = 1 nF -1 3 3 10 20 60 3.8 1.5 10 20 15 300 300 0.8 +1 8 8 40 85 8 8 40 35
trDRVH, tfDRVH tpdhDRVH
25
trDRVL, tfDRVL tpdhDRVL
VCC = PGND CLOAD = 1 nF CLOAD = 1 nF SW = 5 V SW = PGND
150 150 10
SUPPLY VCC Supply Voltage Range Supply Current Normal Mode Shutdown Mode Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis DRV Regulator Output Voltage DRV Regulator Output Current
1 2
VCC IVCC IVCC(SD) VUVLO VDRVREG IDRVREG EN = 5 V EN = 0 V VCC rising CL = 100 nF
22 9.8 5 9.5 600 5.25 12 10 10 5.5
9 5.0 10
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Measured between CSP and CSM. (VCSP - VCSM) = 96 mV x CSADJ/REFIN. 3 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low. 4 The turn-on of DRVL is initiated after DRVH turns off by either SW crossing a ~1 V threshold or by expiration of the timeout delay.
Rev. 0 | Page 4 of 16
ADP3808 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC PGND BST BST to SW SW DRVH DRVL Rating -0.3 V to +25 V -0.3 V to +0.3 V -0.3 V to +30 V -0.3 V to +6 V -4 V to +25 V SW - 0.3 V to BST + 0.3 V PGND - 0.3 V to DRVREG + 0.3 V -25 V to +25 V -0.3 V to VCC + 0.3 V -5 V to +5 V -5 V to +5 V -0.3 V to +6 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SYSP, SYSM to AGND BAT, CSP, CSM to AGND SYSP to SYSM CSP to CSM All Other Inputs and Outputs JA 2-Layer Board 4-Layer Board Operating Ambient Temperature Range Junction Temperature Range Storage Temperature Range Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec)
ESD CAUTION
125C/W 83C/W 0C to 100C 0C to 150C -65C to +150C 300C 215C 220C
Rev. 0 | Page 5 of 16
ADP3808 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
23 SYSM 20 DRVH 24 SYSP 22 VCC 19 BST 18 DRVREG 17 DRVL 16 PGND 15 CSP 14 CSM 13 CSADJ 21 SW
ISYS 1 LIMSET 2 LIMIT 3 EXTPWR 4 RT 5 REFIN 6 AGND 10 CELLSEL 12 BATADJ 7 COMP 9 BAT 11 EN 8
ADP3808
TOP VIEW (Not to Scale)
Figure 2. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 Mnemonic ISYS LIMSET LIMIT EXTPWR Description Output for System Current Sense Amplifier. System Current Limit Set Point Input. System Current Limit Output. This is an open-drain pin and requires a pull-up resistor to a maximum of 6 V. External Adapter Sense Open-Drain Output. This pin pulls low when the ac adapter voltage is present. A pull-up resistor is required to a maximum of 6 V. Frequency Setting Resistor Input. An external resistor connected between this pin and AGND sets the oscillator frequency of the device. Reference Input for BATADJ and CSADJ. Battery Voltage Adjust Input. This pin uses an analog voltage referenced to REFIN to program voltage from 4.0 V to 4.5 V per cell. Charger Enable Input. Pulling this pin to AGND disables the DRVH and DRVL outputs and puts the circuitry powered by VCC into a low power state. The system amplifier and EXTPWR are still active. Output of Error Amplifiers and Compensation Point. Analog Ground. Reference point for the battery sense and all analog functions. Battery Sense Input. Battery Cell Selection Input. Pulling this pin high selects 3-cell operation; pulling it low selects 4-cell operation. Charge Current Programming Input. This pin uses an analog voltage referenced to REFIN to program the battery charge current. (VCSP - VCSM) = 96 mV x CSADJ/REFIN. Negative Current Sense Input. This pin connects to the battery side of the battery current sense resistor. Positive Current Sense Input. This pin connects to the inductor side of the battery current sense resistor. Power Ground. This pin should closely connect to the source of the lower MOSFET. Synchronous Rectifier Drive. Output drive for the lower MOSFET. Driver Supply Output. A bypass capacitor should be connected from this pin to PGND to provide filtering for the low-side supply. Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this bootstrapped voltage for the high-side MOSFET as it is switched. Main Switch Drive. Output drive for the upper MOSFET. Switch Node Input. This pin is connected to the buck-switching node, close to the source of the upper MOSFET, and is the floating return for the upper MOSFET drive signal. Input Supply. This pin does not power the SYS amplifier section. Negative System Current Sense Input. This pin connects to the battery side of the system current sense resistor. Positive System Current Sense Input. This pin connects to the adapter side of the system current sense resistor. This pin also provides power to the system amplifier section. This pin should be connected to AGND.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
RT REFIN BATADJ EN COMP AGND BAT CELLSEL CSADJ CSM CSP PGND DRVL DRVREG BST DRVH SW VCC SYSM SYSP Paddle
Rev. 0 | Page 6 of 16
06632-002
ADP3808 TYPICAL PERFORMANCE CHARACTERISTICS
30 VCC = 16V TA = 25C 25 ON SUPPLY CURRENT (mA)
11
TA = 25C
12
NO LOADS TA = 0C
NUMBER OF PARTS
20
10
15
9
TA = 100C
10
8
5
06632-003
7
06632-008
0 -0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
6 12
13
14
15
VBAT ACCURACY (%)
16 VCC (V)
17
18
19
20
Figure 3. VBAT Accuracy Distribution
Figure 6. On Supply Current vs. VCC
0.15 0.1 0.05 VBAT ACCURACY (%) 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 0
06632-004
126 VCC = 16V 106
TA = 100C
OFF SUPPLY CURRENT (nA)
86
TA = 25C
66
46
TA = 0C
06632-021
26
10
20
30
40 50 60 70 TEMPERATURE (C)
80
90
100
6 12
13
14
15
16 VCC (V)
17
18
19
20
Figure 4. VBAT Accuracy vs. Temperature
Figure 7. Off Supply Current vs. VCC
0.07
0.06 0.05 TA = 25C
20 VCC = 16V TA = 25C fOSC = 300kHz
18
SUPPLY CURRENT (mA)
06632-005
VBAT ACCURACY (%)
0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03
16
14
12
10
06632-009
-0.04 13
0 0 500 1000 1500 2000 2500 DRIVER LOAD CAPACITANCE (pF) 3000
14
15
16 17 VCC (V)
18
19
20
3500
Figure 5. VBAT Accuracy vs. VCC
Figure 8. Supply Current vs. Driver Load Capacitance
Rev. 0 | Page 7 of 16
ADP3808
4.5
400
OSCILLATOR FREQUENCY (kHz)
4
DRIVER ON RESISTANCE ()
VCC = 16V SOURCE
350
3.5 3 2.5 2 SINK
06632-020
300
250
06632-011
1.5 1 0 20 40 60 TEMPERATURE (C) 80
200 90
110
130
150 RT (k)
170
190
210
100
Figure 9. Oscillator Frequency vs. RT
Figure 12. DRVL On Resistance vs. Temperature
6 ISYS RISING ISYS FALLING 5
DRVH 5V/DIV VCC = 16V TA = 25C
4
VLIMIT (V)
3
DRVL 5V/DIV
2
06632-012
200ns/DIV
0
0
0.5
1
1.5 VISYS (V)
2
2.5
3.0
Figure 10. VLIMIT vs. VISYS
Figure 13. Driver Waveforms
3.3 VCC = 16V
CONVERSION EFFICIENCY (%)
100 95 90 85 80 75 70
3.2
DRIVER ON RESISTANCE ()
VCC = 19V VBAT = 12.4V TA = 25C
3.1
3.0
SINK
2.9
SOURCE
06632-013
2.7 0 20 40 60 TEMPERATURE (C) 80
60
100
0
0.5
1.0
1.5
2.0
2.5
3.0
CHARGE CURRENT (A)
Figure 11. DRVH On Resistance vs. Temperature
Figure 14. Conversion Efficiency vs. Charge Current
Rev. 0 | Page 8 of 16
06632-015
2.8
65
06632-014
1
ADP3808
97 96
CONVERSION EFFICIENCY (%)
ICHARGE = 2A
95 94 93 92 91 90
06632-016
ICHARGE = 3A
89 88
3 4 5 6 7 8 VBAT (V) 9 10
VCC = 19V TA = 25C 11 12
13
Figure 15. Conversion Efficiency vs. Battery Voltage
Rev. 0 | Page 9 of 16
ADP3808 THEORY OF OPERATION
The ADP3808 combines a bootstrapped synchronous switching driver with programmable current control and accurate final battery voltage control in a constant-current, constant-voltage (CCCV) Li-Ion battery charger. High accuracy voltage control is needed to safely charge Li-Ion batteries, which are typically specified at 4.2 V 1% per cell. For a typical notebook computer battery pack, three or four cells are in series, giving a total voltage of 12.6 V or 16.8 V. The ADP3808 allows the final battery voltage to be programmed. The programmable range is 4.0 V to 4.5 V per cell. The total number of cells to be charged can be set to either 3 or 4 via a control pin. Another requirement for safely charging Li-Ion batteries is accurate control of the charge current. The actual charge current depends on the number of cells in parallel within the battery pack. Typically, this is in the range of 2 A to 3 A. The ADP3808 provides flexibility in programming the charge current over a wide range. An external resistor is used to sense the charge current. The charge current can be set by programming the sense resistor voltage drop. The voltage drop can be set to a maximum of 96 mV. This programmability allows the current to be changed during charging. For example, the charge current can be reduced for trickle charging. The synchronous driver provides high efficiency when charging at high currents. Efficiency is important mainly to reduce the amount of heat generated in the charger, but also to stay within the power limits of the ac adapter. With the addition of a bootstrapped high-side driver, the ADP3808 drives two external power NMOS transistors for a simple, lower cost power stage. The ADP3808 also provides an uncommitted current sense amplifier. This amplifier provides an analog output pin for monitoring the current through an external sense resistor. The amplifier can be used anywhere in the system that high-side current sensing is needed. The sense amplifier output is compared to a programmable voltage limit. If the limit is exceeded, the LIMIT pin is asserted. The system sense amplifier is also used to detect the presence of an ac adaptor. If the adaptor is detected, the ADP3808 asserts a logic pin to signal the detection.
SETTING THE CHARGE CURRENT
The charge current is measured across an external sense resistor, RCS, between the CSP and CSM pins. The input common-mode range is from ground to VCC, allowing current control in short-circuit and low dropout conditions. The voltage between CSP and CSM is programmed by a ratio of the voltages at CSADJ and REFIN according to Equation 1.
VCSP - VCSM = 96 mV CSADJ REFIN
(1)
For example, using a 20 m sense resistor gives a range from 150 mA with CSADJ = REFIN/32 to 4.8 A maximum when CSADJ = REFIN. The power dissipation in RCS should be kept below 500 mW. Components R4 and C13 provide high frequency filtering for the current sense signal.
Rev. 0 | Page 10 of 16
ADP3808
RSS 10m 1/2 Q1 FD56990A R13 10 C15 22F + - 1/2 Q1 FD56990A L1 22H + C16 - 22F C13 22F RCS 20m R4 510 C1 2.2F R2 510 3.3V SYSTEM DC/DC
VIN
BATTERY 12.6V/16.8V
C14 2.2F VCC BST
C9 100nF DRV
SW
DRVL
PGND
CSP
CSM
SYSP
SYSM
ISYS
LIMIT 3.3V
AMP2
EN VREF + VREG UVLO BIAS
IN DRVLSD
DRVLSD - + - - 1V SYSP BAT CHARGE CURRENT SETPOINT + - +
DRVREG 7.0V C10 0.1F EN
VTH
+ - LOGIC CONTROL
gm1
+ CSADJ BAT 3.3V 3-/4-CELL SELECTION BATTERY VOLTAGE ADJUST CELLSEL R8 56 R11 REFIN BATADJ R12
OSCILLATOR
gm2
-
ADP3808
+
AGND
RT 150k
COMP C8 0.22F C11
Figure 16. Typical Application Circuit
FINAL BATTERY VOLTAGE CONTROL
As the battery approaches its final voltage, the ADP3808 switches from CC mode to CV mode. The change is achieved by the common output node of gm1 and gm2. Only one of the two outputs controls the voltage at the COMP pin. Both amplifiers can only pull down on COMP, such that when either amplifier has a positive differential input voltage, its output is not active. For example, when the battery voltage, VBAT, is low, gm2 does not control VCOMP. When the battery voltage reaches the desired final voltage, gm2 takes control of the loop, and the charge current is reduced. Amplifier gm2 compares the battery voltage to a programmable level set by pins BATADJ and REFIN. The target battery voltage is dependent on the state of the CELLSEL pin as CELLSEL sets the number of cells to be charged. Pulling CELLSEL high sets the ADP3808 to charge three cells. When CELLSEL is tied to ground, four cells are selected. CELLSEL has a 2 A pull-up current as a fail-safe to select three cells when it is left open. The final battery voltage is programmable from 4.0 V to 4.5 V per cell. The programming voltage is applied to the BATADJ pin
and is ratioed to the REFIN pin. The battery voltage VBAT is set according to Equation 2 and Equation 3. For CELLSEL > 2 V:
VBAT = 12 V + 1.5 V
For CELLSEL < 0.8 V:
BATADJ REFIN
06632-018
VBAT = 16 V + 2 V
OSCILLATOR AND PWM
The oscillator generates a triangle waveform between 1 V and 2 V, which is compared to the voltage at the COMP pin, setting the duty cycle of the driver stage. When VCOMP is below 1.0 V, the duty cycle is zero. Above 2.0 V, the duty cycle reaches its maximum. The oscillator frequency is set by the external resistor at the RT pin, ROSC, and is given by Equation 4.
f OSC =
41 x 10 9 ROSC
Rev. 0 | Page 11 of 16
+
-
BOOTSTRAPPED SYNCHRONOUS DRIVER
+- AMP1
-
+ LIMSET
R9
R10 EXTPWR
(2)
BATADJ REFIN
(3)
(4)
ADP3808
DRVREG
ADP3808
BOOTSTRAPPED SYNCHRONOUS DRIVER BST CMP3 CBST IN MIN OFF TIME DRVH
Q1
EN SW - CMP2 +
DELAY
1V
1V
- CMP1 + DELAY
DRVL PGND
Q2
Figure 17. Bootstrapped Synchronous Driver
5.25 V BOOTSTRAP REGULATOR
The driver stage is powered by the internal 5.25 V bootstrap regulator, which is available at the DRVREG pin. Because the switching currents are supplied by this regulator, decoupling must be added. A 0.1 F capacitor should be placed close to the ADP3808, with the ground side connected close to the power ground pin, PGND. This supply is not recommended for use externally due to high switching noise.
Overlap protection is included in the driver to ensure that both external MOSFETs are not on at the same time. When DRVH turns off the upper MOSFET, the SW node goes low due to the inductor current. The ADP3808 monitors the SW voltage, and DRVL goes high to turn on the lower MOSFET when SW goes below 1 V. When DRVL turns off, an internal timer adds a delay of 50 ns before turning DRVH on. When the charge current is low, the DRVLSD comparator signals the driver to turn off the low-side MOSFET and DRVL is held low. The DRVLSD threshold is set to 0.8 V corresponding to a 32 mV differential between the CS pins. The driver stage monitors the voltage across the BST capacitor with CMP3. When this voltage is less than 4 V, CMP3 forces a minimum off time of 200 ns. This ensures that the BST capacitor is charged even during DRVLSD. However, because a minimum off time is only forced when needed, the maximum duty cycle is greater than 99%.
BOOTSTRAPPED SYNCHRONOUS DRIVER
The PWM comparator controls the state of the synchronous driver shown in Figure 17. A high output from the PWM comparator forces DRVH on and DRVL off. The drivers have an on resistance of less than 4 for fast rise and fall times when driving external MOSFETs. Furthermore, the bootstrapped drive allows an external NMOS transistor for the main switch instead of a PMOS. A boost capacitor of 0.1 F must be added externally between BST and SW. The DRVL pin switches between DRVREG and PGND. The 5.25 V output of DRVREG drives the external NMOS with high VGS to lower the on resistance. PGND should be connected close to the source pin of the external synchronous NMOS. When DRVL is high, this turns on the lower NMOS and pulls the SW node to ground. At this point, the boost capacitor is charged up through the internal boost diode. When the PWM switches high, DRVL is turned off and DRVH turns on. DRVH switches between BST and SW. When DRVH is on, the SW pin is pulled up to the input supply (typically 16 V), and BST rises above this voltage by approximately 4.75 V.
SYSTEM CURRENT SENSE
An uncommitted differential amplifier is provided for additional high-side current sensing. This amplifier, AMP2, has a fixed gain of 50 V/V from the SYSP and SYSM pins to the analog output at ISYS. ISYS has a 100 A source capability to drive an external load. The common-mode range of the input pins is from 10 V to 22 V. This amplifier is the only part of the ADP3808 that remains active during shutdown. The power to this block is derived from the bias current on the SYSP and SYSM pins.
Rev. 0 | Page 12 of 16
06632-019
DRVLSD
ADP3808
LIMIT
The LIMIT pin is an open-drain output that signals when the voltage at ISYS exceeds the voltage at LIMSET. The internal comparator produces the function shown in Figure 10. This is a graph of VLIMIT vs. VISYS where LIMSET is set to 1.5 V. The LIMIT pin should be pulled up to a maximum of 6 V through a resistor. When ISYS is below LIMSET, the LIMIT pin has high output impedance. The open-drain output is capable of sinking 700 A when the threshold is exceeded. This comparator is turned off during shutdown to conserve power.
UVLO
Undervoltage lock-out, UVLO, is included in the ADP3808 to ensure proper startup. As VCC rises above 1 V, the regulator tracks VCC until it reaches its final voltage. However, the rest of the circuitry is held off by the UVLO comparator. The UVLO comparator monitors the regulator to ensure that it is above 5 V before turning on the main charger circuitry. This occurs when VCC reaches 9.5 V. Monitoring the regulator outputs makes sure that the charger circuitry and driver stage have sufficient voltage to operate normally. The UVLO comparator includes 600 mV of hysteresis to prevent oscillations near the threshold.
AC ADAPTOR DETECTION
The EXTPWR pin on the ADP3808 is an open-drain active low output used to signal that an ac adaptor is connected. If the ISYS voltage level is greater than 1 V or the SYSP sense pin voltage is greater then 18.25 V, the EXTPWR pin is driven low. A pull-up resistor must be connected when this function is required. The maximum pull-up voltage is 6 V.
LOOP FEED FORWARD
As the startup sequence discussion shows, the response time at COMP is slowed by the large compensation capacitor. To speed up the response, two comparators can quickly feed forward around the normal control loop and pull the COMP node down to limit any overshoot in either short-circuit or overvoltage conditions. The overvoltage comparator has a trip point set to 35% higher than the final battery voltage. The overcurrent comparator threshold is set to 100 mV across the CS pins. When these comparators are tripped, a normal soft start sequence is initiated. The overvoltage comparator is valuable when the battery is removed during charging. In this case, the current in the inductor causes the output voltage to spike up, and the comparator limits the maximum voltage. Neither of these comparators affects the loop under normal charging conditions.
EN
A high impedance CMOS logic input is provided to turn off the ADP3808. When the voltage on EN is less than 0.8 V, the ADP3808 is placed in low power shutdown. With the exception of the system current sense amplifier, AMP2, all other circuitry is turned off. The reference and regulators are pulled to ground during shutdown and all switching is stopped. During this state, the supply current is less than 5 A. In addition, the BAT, CSP, CSM, and SW pins go to high impedance to minimize current drain from the battery.
Rev. 0 | Page 13 of 16
ADP3808 APPLICATION INFORMATION
DESIGN PROCEDURE
Refer to Figure 16, the typical application circuit, for the following description. The design follows that of a buck converter. With Li-Ion cells it is important to have a regulator with accurate output voltage control. input capacitor has to absorb this current ripple, it must have an appropriate rms current rating. The maximum input rms current is given by
I rms = PBAT x D VIN
x
D(1 - D) D
(10)
BATTERY VOLTAGE SETTINGS
Inductor Selection
Usually the inductor is chosen based on the assumption that the inductor ripple current is 15% of the maximum output dc current at maximum input voltage. As long as the inductor used has a value close to this, the system should work fine. The final choice affects the trade-offs between cost, size, and efficiency. For example, the lower the inductance, the size is smaller but ripple current is higher. This situation, if taken too far, leads to higher ac losses in the core and the windings. Conversely, a higher inductance results in lower ripple current and smaller output filter capacitors, but the transient response will be slower. With these considerations, the required inductance can be calculated using Equation 6.
L1 = VIN , MAX - VBAT I x D MIN x TS
where is the estimated converter efficiency (approximately 90%, 0.9) and PBAT is the maximum battery power consumed. This is a worst-case calculation and, depending on total charge time, the calculated number could be relaxed. Consult the capacitor manufacturer for further technical information.
Decoupling the VCC Pin
It is a good idea to use an RC filter (R13 and C14) from the input voltage to the IC both to filter out switching noise and to supply bypass to the chip. During layout, this capacitor should be placed as close to the IC as possible. Values between 0.1 F and 2.2 F are recommended.
Current Sense Filtering
During normal circuit operation, the current sense signals can have high frequency transients that need filtering to ensure proper operation. In the case of the CSP and CSM inputs, Resistor R4 is set to 510 and the filter capacitor C13 is 22 nF. For the system current sense filter on SYSP, SYSM, R2 is set to 510 , C1 is 2.2 F, and C2 is 470 nF.
(6)
where the maximum input voltage VIN, MAX is used with the minimum duty ratio DMIN. The duty ratio is defined as the ratio of the output voltage to the input voltage, VBAT/VIN. The ripple current is calculated using Equation 7. I = 0.3 x IBAT, MAX The maximum peak-to-peak ripple is 30%, that is 0.3, and maximum battery current, IBAT, MAX, is used. For example, with VIN, MAX = 19 V, VBAT = 12.6 V, IBAT, MAX = 3A, and TS = 4 s, the value of L1 is calculated as 18.9 H. Choosing the closest standard value gives L1 = 22 H. (7)
MOSFET Selection
One of the features of the ADP3808 is that it allows use of a high-side NMOS switch instead of a more costly PMOS device. The converter also uses synchronous rectification for optimal efficiency. To use a high-side NMOS, an internal bootstrap regulator automatically generates a 5.25 V supply across C9. Maximum output current determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3808 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the load current. The power dissipation for each MOSFET is given by Upper MOSFET:
PDISS = RDS(ON) x (IBAT x D)2 + VIN x IBAT x D x TSW x f (11)
Output Capacitor Selection
An output capacitor is needed in the charger circuit to absorb the switching frequency ripple current and smooth the output voltage. The rms value of the output ripple current is given by
I rms = VIN , MAX fL1 12 D (1 - D )
(8)
The maximum value occurs when the duty cycle is 0.5. Thus,
I rms _ MAX = 0.072 VIN , MAX fL1
Lower MOSFET: (9)
PDISS = RDS(ON) x (IBAT x D)2 + VIN x (IBAT x 1 - D)2 x tSW x f (12)
For an input voltage of 19 V and a 22 H inductance, the maximum rms current is 0.26 A. A typical 10 F or 22 F ceramic capacitor is a good choice to absorb this current.
where f is the switching frequency and tSW is the switch transition time, usually 10 ns. The first term accounts for conduction losses while the second term estimates switching losses. Using these equations and the manufacturer's data sheets, the proper device can be selected.
Input Capacitor Ripple
As is the case with a normal buck converter, the pulse current at the input has a high rms component. Therefore, because the
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ADP3808 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP
19 18 EXPOSED PAD
(BOTTOM VIEW)
PIN 1 INDICATOR
24 1
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
2.25 2.10 SQ 1.95
7 6
13 12
0.25 MIN 2.50 REF
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 20. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-24-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3808JCPZ 1 ADP3808JCPZ-RL1
1
Temperature Range 0C to 100C 0C to 100C
Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option CP-24-1 CP-24-1
Ordering Quantity
5000
Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
ADP3808 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06632-0-6/07(0)
Rev. 0 | Page 16 of 16

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